1. Field of the Invention
The present invention relates generally to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device having a recess gate for improving reliability of the semiconductor device.
2. Description of the Prior Art
In general, as semiconductor devices are highly integrated, the gate channel lengths of the highly integrated semiconductor devices are significantly shortened. For this reason, the charge-sharing phenomenon frequently occurs between the source and drain areas of a gate (collectively referred to as the “source/drain area”) contributing to degradation of the gate control function—this is known as a “short channel effect”. Due to the short channel effect, a threshold voltage (Vt) is significantly lowered and a drain induced barrier lowering (DIBL) effect is generated, causing problems when the semiconductor devices are operated.
In addition, with increasing degree of high integration in a semiconductor device, more ions are excessively implanted into the source/drain area, and the depth of the source/drain area becomes shallow. This causes the spiking phenomenon and increases the parasitic series resistance. When the spiking phenomenon occurs, the source/drain area of a gate rarely performs its intended functions, because the silicon layer in a junction area is reacted with metallic materials when the source/drain area makes contact with the metallic materials.
In addition, since the thickness of the silicon layer of the junction area is thin, the resistance applied to the silicon layer is increased, so that the parasitic series resistance is also increased. If the parasitic series resistance is increased, the actual voltage difference between the source area and the drain area is reduced, so that a relatively high voltage is required for operating the semiconductor device.
In order to prevent the short channel effect and the spiking phenomenon and to lower the parasitic series resistance, various semiconductor fabrication technologies capable of lengthening an effective line width of a channel and enlarging the thickness of a silicon layer in the source/drain area have been developed.
For example, a recess gate forming technology and a buried gate forming technology are suggested by prior art. According to the recess gate forming technology, a recess is formed in a semiconductor substrate and a gate is formed in the recess, thereby enlarging the thickness of the silicon layer in the source/drain area. According to the buried gate forming technology, a gate is formed in the semiconductor substrate in such a manner that the thickness of a silicon layer in a junction area can be enlarged while lengthening the effective length of a channel.
Hereinafter, the conventional recess gate forming technology and the conventional buried gate forming technology will be briefly described.
FIGS. 1A and 1B are cross-sectional views for illustrating the procedure for manufacturing a semiconductor device through the conventional recess gate forming technology.
Referring to FIG. 1A, a pad oxide layer 2 and a pad nitride layer 3 are sequentially formed on a semiconductor substrate 1. Then, the pad nitride layer 3 and the pad oxide layer 2 are etched such that a gate area is exposed. After that, the exposed area of the semiconductor substrate 1 is locally thermal-oxidized through a local oxidation of silicon (LOCOS) process, thereby growing an oxide layer 4 as shown in FIG. 1A.
Referring to FIG. 1B, a portion of the oxide layer 4 is recessed by a predetermined depth. Then, a conductive layer 5 and a hard mask layer 6 are filled in the recessed area, thereby forming a gate 7. After that, the pad oxide layer 3 is removed, and a spacer 8 is formed at both sidewalls of the gate 7. Then, a source/drain ion implantation process is performed, thereby forming a source/drain area 9 below the upper surface of the semiconductor substrate 1 at each side of the gate 7.
After that, although not shown in the figures, other fabrication processes are subsequently performed to complete the semiconductor device fabrication.
FIG. 2 is a cross-sectional view for illustrating the procedure for manufacturing a semiconductor device through the conventional buried gate forming technology.
As shown in FIG. 2, after recessing a gate area of a semiconductor substrate 21 by a predetermined depth, a gate 24 including a gate insulating layer 22 and a gate conductive layer 23 is formed in the recessed area of the semiconductor substrate 21. Then, a source/drain ion implantation process is performed, thereby forming a source/drain area 25 on an upper surface of the semiconductor substrate 21 at both sides of the gate 24.
After that, a predetermined upper portion of the gate 24 and a predetermined portion of the semiconductor substrate 21 formed at both sides of the gate 24 are etched, and a capping insulating layer 26 is formed or “buried” in the etched area. The capping insulating layer 26 protects the gate 24 and insulates the source area from the drain area.
Then, although not shown in the figures, other fabrication processes are subsequently performed to complete the semiconductor device fabrication.
However, according to the conventional recess gate forming technique as in the case of FIGS. 1A-1B, the size of the step difference between the channel area and the source/drain area may depend on the amount of the semiconductor substrate 1, some of which constituting the channel area is lost when the oxide layer 4 is grown into the substrate 1. Thus, it is difficult to sufficiently enlarge the step difference size between the channel area and the source/drain area by utilizing the conventional recess gate forming techniques. Therefore, there are limitations to reduce the parasitic series resistance and spiking phenomenon. In addition, when the oxide layer 4 is grown through the LOCOS process, an unwanted deposition resembling a bird's beak (not shown) is formed at each of the end portions of the oxide layer, so there is limitation to reduce the line width of the gate.
As in the case of FIG. 2, although the conventional buried gate forming technology can effectively lengthen the effective line width of a gate 24, all of the overlap area of the gate, the insulating layer, and the silicon layer are enlarged at both sides of the gate, so the parasitic series resistance of a transistor fabricated through the conventional buried gate forming technology is higher than that of a transistor having a planar channel structure by at least 50%. Accordingly, an RC delay may occur in the semiconductor device fabricated through the conventional buried gate forming technology, so the semiconductor device fabricated through the conventional buried gate forming technology is not adaptable for high-speed operation.
In particular, according to the semiconductor device fabricated through the conventional buried gate forming technology, the thickness of the gate insulating layer may become thin at a gate edge, thereby causing the inferior gate induced drain leakage (GIDL) characteristics. In addition, since the electric field is dispersed at a channel edge part, it is difficult to realize the channel at the channel edge part, so that the parasitic series resistance may increase, thereby causing the inferior current characteristic.
Furthermore, the above-mentioned conventional techniques cannot efficiently restrict the punch-through phenomenon causing an undesired current flow between source/drain areas, so reliability of the semiconductor device, such as the operational characteristic of the semiconductor device, may be degraded.